SMART VLSI is well-positioned to support customers at any point and any level of Semiconductor product life cycle. Our Team exposure to various Processes, Foundries and EDA tools as an added advantage for shorter turn-around time for customers production release and Time to market.
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SYNTHESIS
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Introduction to Synthesis and Synthesis Flow
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Constraining Design for timing area and power
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Understanding .libs and Exploring .lib
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Synthesize Design and Timing Checks
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Analyzing Timing Reports and debug results
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Area Optimization Techniques
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Low Power Synthesis using UPF
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Understanding the UPF and low power concepts
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Understanding of Low power cells and their requirement
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Low power synthesis using UPF file
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Scan Insertion
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PHYSICAL DESIGN
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Digital Electronics fundamentals.
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CMOS fundamentals.
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LINUX Verilog / VHDL Knowledge
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ASIC / SOC design flows
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Physical Design Inputs and Sanity Check
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Floorplan Power Routing
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Placement Timing Analysis and Optimization
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Clock Tree Synthesis
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Routing ECO Flows
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All Sign-off Checks Covering PhysicalDesign Project from Netlist to GDS flow
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STA
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Introduction to STA and concepts
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Clocking:
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Handling clock muxes Clock dividers
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Clock dividers
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Generated clocks,
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Clocking Exceptions
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Timing Exceptions
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Post Layout STA using SPEF
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Multi-Mode and Multi Corner STA
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Derates, OCV, Variations
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Crosstalk and Noise Analysis
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What-If Analysis
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Timing ECOs generation
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Timing Challenges
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DFT
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DFT Basics
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SCAN and JTAG Insertion
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Scan architecture overview and Understanding of SCAN in depth
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Understanding and analysis of DFT DRC
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Full scan insertion and stitching without compression
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Generate test protocol and understanding
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Scan insertion with compression
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Boundary scan basics and Boundary scan cell operation in detail
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ATPG and Different types of ATPG
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❖Understanding of ATPG constraints
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Understanding of Silicon testing from Tester to gate level
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❖Fault Detection
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Test Coverage Vs Fault Coverage
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ATPG pattern simulation flow & Coverage improvement techniques
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Formal Verification
❖ Understanding and Matching compare points
❖How to Verify the design
❖ Interpreting results
❖Debugging Verification
❖Verifying the implemented reference design
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Course Duration
❖ 3 months
Placement statistics:
❖ 100% Placement