Careers
- Associate Engineer
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Job Description
B.Tech Electronics/Electrical/Computer Science Engineering with minimum of 6 months training in VLSI courses with high scores. Or M.Tech in Electronics/VLSI/CAD with good % of marks
Experience Required : 0-1 Year
Skills Required
- Strong analytical/Aptitude skills.
- Very good programming & scripting skills.
- Excellent skills in Unix, Shell
- Good communication & very good attitude.
Location: Bangalore
send your resumes to hr@smartvlsi.com
- Physical Design Engineer
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Job Description
B.Tech or M.Tech in Electronics/Electrical Engineering with minimum of 1 year of strong, hands on Physical Design experience. Must have handled Netlist to GDS II at block level for multiple tape outs. With Block level hands on experiences in most of the following:.
Experience Required: 2-4 yrs
Skills Required
- Block level floor planning, power planning and IR drop analysis.
- Timing closure with Xtalk and OCV
- Multimode multi corner optimization and closure.
- Clock tree synthesis and advanced clock tree implementation.
- Blocks sizes upward of 400K Instances to 2M Instances.
- Block level timing closure with sign off STA.
- Block level ECO implementation involving netlist level logical changes.
- Scripting experience in Perl/TCL.
- Excellent debugging skills in implementation issues and ability to come up with creative solutions.
- Low power technologies exposure.
- Technologies from 28nm and below.
- Physical Verification experience in advance nodes.
Location: Bangalore, Hyderabad, Chennai and Delhi
send your resumes to hr@smartvlsi.com
- Sr Lead Physical Design
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Job Description
B.Tech or M.Tech in Electronics/Electrical Engineering with minimum of 6 years of strong, hands on Physical Design experience. Must have handled Netlist to GDS II at Top level or Hierarchical top level for at least 1 tape out. Must have lead physical design team with hands on exposure in most of the following depending up on senior level or lead level role. Should have experience in 28nm & below technologies experience in 10nm & below is an added advantage
Experience Required: 5-10 yrs
Skills Required
- Top level die size estimation, floor planning, power estimation , power planning .
- IO Planning and package compatibility sign off.
- Netlist and constraint sign in checks and validation.
- Prime time constraint development at full chip level and clean up.
- Design implementation environment setup.
- Static and Dynamic power analysis at the top level.
- Netlist to GDS II implementation at chip level.
- Hierarchical chip planning, block planning , block level constraint development, hierarchical clock tree implementation, block integration and chip finishing.
- Multimode multi corner optimization and closure at top level.
- Clock tree synthesis and advanced clock tree implementation at full chip level.
- Handling of PLL, TXR, DDR and other analog components during implementation.
- IO ring customization for multi IO designs.
- Full chips upward of 1M Instances to 20M+ instances.
- Top level timing closure with sign off STA in MMMC with Xtalk and OCV.
- Top level ECO implementation strategy development for netlist ,RTL and timing level changes
- Scripting experience in Perl/TCL.
- Flow customization and fine tuning for Power , Performance, Area.
- Exposure to DFM and DFM compatible implementation.
- Excellent debugging skills in implementation issues and ability to come up with creative solutions .
- Exposure to designs critical for power, area and timing at the same time.
- Technologies from 28nm and below.
- Exposure to Physical design project planning and execution.
- Technical leadership and ability to mentor and make the team deliver.
Location: Bangalore
send your resumes to hr@smartvlsi.com
Location: Bangalore, Hyderabad, Chennai and Delhi
send your resumes to hr@smartvlsi.com
- Floorplan lead
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Job Description
B.Tech or M.Tech in Electronics/Electrical Engineering with minimum of 6 years of strong, hands on Physical Design experience. Must have hands in hierarchical partitioning of internal hard macros/blocks from either chip top or sub system. Should have experience in 28nm & below technologies experience in 10nm & below is an added advantage
Skills Required
- hierarchical partitioning of internal hard macros/blocks from either chip top or sub system
- Top level die size estimation, floor planning, power estimation , power planning .
- Handling of PLL, TXR, DDR and other analog components during implementation.
- Scripting experience in Perl/TCL.
- Flow customization and fine tuning for Power , Performance, Area.
- Exposure to DFM and DFM compatible implementation.
- Excellent debugging skills in implementation issues and ability to come up with creative solutions .
- Exposure to designs critical for power, area and timing at the same time.
- Technologies from 28nm and below.
- Exposure to Physical design project planning and execution.
- Technical leadership and ability to mentor and make the team deliver.
Location: Bangalore, Hyderabad, Chennai and Delhi
send your resumes to hr@smartvlsi.com
- STA Lead : Static Timing Analysis
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Job Description
B.Tech or M.Tech in Electronics/Electrical Engineering with minimum of 6 years of strong, hands on block/sub HM level Timing closure or chip top level timing closure. Should have experience in 28nm & below technologies experience in 10nm & below is an added advantage
Skills Required
- Netlist and constraint sign in checks and validation.
- Prime time constraint development at full chip level and clean up.
- Multimode multi corner timing knowledge and timing closure at sub HM/block/top level.
- Top level timing closure with sign off STA in MMMC with Xtalk and OCV.
- Top level ECO implementation strategy development for netlist, RTL and timing level changes
- Scripting experience in Perl/TCL.
- Excellent debugging skills in implementation issues and ability to come up with creative solutions .
- Technologies from 28nm and below.
- Technical leadership and ability to mentor and make the team deliver.
Location: Bangalore, Hyderabad, Chennai and Delhi
send your resumes to hr@smartvlsi.com
- ASIC verification Engineer
Job Description
Candidate will be responsible for IP Level Verification. Engineer should independently be able to own the verification of IP level modules end to end with continuous enhancements.
Skills Required
- Minimum Qualifications Desired skills set includes Verification aptitude, Expertise in SV-UVM, Coverage Closure, RTL debug till root causing, Low Power Verification/UPF, GLS, Assertions based verification, DPI, Testbench building.
- Familiarity with bus protocols like AHB, AXI, ARM based system architecture, emulation (ex: Veloce), Scripting language like perl
- Excellent problem solving skills and strong communication and team work skills are mandatory
- Preferred Qualifications Formal Verification concepts and working knowledge, C/C++, working knowledge on camera are plus
- BE/BTech/ME/MTech/MS Electrical Engineering and/or Electronics, Vlsi from reputed university with preferably distinction
Education Requirements Required:
Location: Bangalore, Hyderabad, Chennai, Delhi
send your resumes to hr@smartvlsi.com
- Layout Engineer
Job Description
Hands on experience with layouts of important memory building blocks like control, sense amplifiers, I/O Blocks, bit cell array and decoders etc in compiler context. Should have worked on 16nm / 14nm / 10nm/ 7nm/ Finfet process technologies . Hands on experience with top level memory integration and DRC, LVS, Density verification and cleaning physicals across the compiler space. Good handle on IR/EM related issues in memory layouts.
Experience Required: 2-4 yrs
Skills Required
- Must have worked on cadence tools for layout design and Cadence/Mentor/Synopsys tools for physical verification checks.
- Strong knowledge of ultra-deep sub-micron layout design related challenges and good understanding of DFM guidelines.
- Experience & or strong interest in memory compilers developed.
- Excellent and demonstrated team player with ability to work with external customers and in cross functional teams.
Location: Bangalore
send your resumes to hr@smartvlsi.com
- Senior Analog Design Engineers
Job Description
Candidate will work on design, verification, modelling of various analog and mixed signal blocks like amplifiers, references, regulators (LDO/DCDC - Buck, Boost, Multiphase), oscillators, POR-POK across a wide range of technologies. Will have to interface with layout and mixed signal verification teams to ensure ontime, bug-free customer deliveries. Must be technically independent, and able to work in a multi-site team environment. Strong verbal & written communication skills are desired.
Experience Required: 3-8 yrs
Skills Required
- Bachelors in Electronics &Telecommunication/ Electrical
- PG : Masters in Electronics & Telecommunication/VLSI
- Must be strong in basics of R,L,C, Network Theory, Signals & Systems, Control theory, Device fundamentals.
- Must have hands-on working knowledge in analog circuit design, with special emphasis on Power Management (blocks like LDO, DCDC, POR/POK, Bandgap Reference).
- Should be well-versed with industry standard EDA flows of Cadence/Mentor Graphics/Synopsys.
- Basic knowledge of analog layout is needed. Knowledge of scripting languages (Perl, TCL, Skill, Ocean) is an added advantage.
- Block level ECO implementation involving netlist level logical changes.
- Scripting experience in Perl/TCL.
- Excellent debugging skills in implementation issues and ability to come up with creative solutions.
- Low power technologies exposure.
- Technologies from 28nm and below.
- Physical Verification experience in advance nodes.
Location: Bangalore, Hyderabad and Chennai
send your resumes to hr@smartvlsi.com