FROENTEND DESIGN SUPPORT:
RTL
- Design
- Top integration
- Verification
SYNTHESIS
- Logic synthesis
- Physical Synthesis
- Owning Design Constraints development and signoff Activity
FORMAL VERIFICATION
PHYSICAL DESIGN SERVICES
- Chip Hierarchical Partitioning
- Owning Subsystem Floorplan
- Floorplan
- Placement
- CTS (Full Chip/Block level Design)
- Signal Routing and Optimization
- DFM
- ECOS
STA
- Constraints Signoff
- IO budgeting
- With OCV and other industry methods
- STA on FULL CHIP and SUB SYTEMS
DFT SUPPORT
DFT ARCHITECHTURE
- SCAN
- MBIST
- Boundary Scan
- ATPG Flat / Hierarchical Partition
TEST PROGRAMS
- Advance fault model
- Implementation and validation
VERIFICATION AND VALIDATION
- Formal Verification
- IP--SOC Functional Verification
- Low Power Verification
- Analog Mixed Signals Verification
- Post Silicon Validation
SIGNOFF CHECKS
- POWER/EM/IR
- Formal Verification
- Conformal Verification
- Physical Verification (FULL CHIP/ IP)